Designing an Optimal SRAM Memory With Low Power Consumption Within the 65-Nanometer Technology

Today, with the development of the semi-conductive devices building technology, the speed and power consumption parameters play a major role in increasing the electronic devices capability and speed. The electronic chips with high speed and low power consumption have always been of interest to the military industries and research and commercial centers. On the other hand, the SRAM memories are considered as one main part on the SOCs circuits. The SRAM memories waste a considerable amount of power consumption (around 45%) in computer systems. Hence, the power consumption reduction techniques should be employed besides considering this issue.In this research, first the SRAM cell and various cells that were designed and proposed for SRAM memories to date are introduced. In order to examine various parameters of the SRAM cell such as speed, power consumption, propagation delay, distortion and also the utilization of different techniques towards improving the performance and reducing the power consumption, the suggested memory cell was simulated in the Hspice environment. The obtained results are compared to other memory cells architectures. The research results confirm the suggested model of the present research.

Keywords:

Memory blocks , SoCs circuits , SRAM memories , power consumption , leaking current , Hspice