Design of New Full-Swing and Energy-Efficient Full Adder for Low- Power and Low-Voltage Designs

This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The proposed full adder design exhibits low PDP, full-swing operation, excellent driving capabilities. The new full adder has also excellent performance at low values of power supply, so this circuit is a suitable choice for low-power applications and low-voltage designs. According to the simulation results, the proposed full adder has the bestpower consumption, propagation delay and power-delay product compared to its counterparts, such that the power-delay product of the proposed full adder is 30% better than the next best PDP. HSPICE simulations using TSMC 0.18-μm technology with a power supply of 1.8V was utilized to evaluate the performance of the circuits.

Keywords:

Full Adder , High-Performance , Hybrid- CMOS , Low-Power , Low-Voltage , VLSI