Exploring the VLIW Architecture Space for Network Applications
Publish place: Journal of Computer and Robotics، Vol: 3، Issue: 2
Publish Year: 1388
نوع سند: مقاله ژورنالی
زبان: English
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شناسه ملی سند علمی:
JR_JCR-3-2_006
تاریخ نمایه سازی: 23 دی 1396
Abstract:
The increasing diversity in packet-processing applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. Also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. This paper reports on extensive simulation experiments carried out for exploring the performance of instruction-level parallel Very Long Instruction Word (VLIW) processors executing packet-processing applications. On the grounds of the experimental results, a design space exploration has been used to derive an efficient application-specific VLIW processor architecture based on the VEX instruction set architecture. The VEX simulator toolset has been used for design space exploration, and a number of networking applications have been chosen to serve in guiding the architectural exploration. The optimization measures achieve up to 60% improvement in performance for the most representative packet-processing applications.
Authors
Mostafa E. Salehi
Islamic Azad University, Qazvin Branch, Qazvin, Iran
Ali Torabi
Islamic Azad University, Qazvin Branch, Qazvin, Iran
Abolfazl Salarian
Islamic Azad University, Qazvin Branch, Qazvin, Iran