New high-performance majority function based Full Adders
Publish place: 14th annual International CSI Computer Conference
Publish Year: 1388
نوع سند: مقاله کنفرانسی
زبان: English
View: 2,549
This Paper With 5 Page And PDF Format Ready To Download
- Certificate
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
CSICC14_027
تاریخ نمایه سازی: 24 خرداد 1388
Abstract:
Two new high-performance Full Adders, purely designed with 3-input Majority-not function, are proposed in this paper. The Majority-not function is implemented efficiently by using only capacitors and a static CMOS inverter. This kind of design improves the parameters of the Full Adder cell and leads to high performance, driving capability, a high degree of regularity and simplicity. Five state-of-the-art 1-bit Full Adder cells and the proposed Full Adders are simulated using 0.18μm CMOS technology at three supply voltages. Simulation results demonstrate significant improvement in terms of power consumption and Power-Delay Product (PDP).
Keywords:
Authors
Mohammad Hossein Moaiyeri
Science and Research Branch of Islamic Azad University, Tehran, Iran
Reza Faghih Mirzaee
Science and Research Branch of Islamic Azad University,Tehran, Iran
Keivan Navi
Shahid Beheshti University, G. C., Tehran, Iran
Tooraj Nikoubin
Shahid Beheshti University, G. C., Tehran, Iran