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Journal Paper
طراحی و شبیه سازی یک واحد حساب و منطق 64×64 بیتی با سرعت کلاک 2 گیگا هرتز در تکنولوژی 130 نانومتر
Authors:
مریم سیستانی زاده
،
رضا حسینی
Year 1399
Publish place:
Journal of Iranian Association of Electrical and Electronics Engineers Issue 1، Vol 18
Pages:
11
| Language: Persian
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Conference Paper
A 32-bit pipeline phase accumulator with clock division technique at 0.5μm CMOS technology
Authors:
Amir Tarvirdi
،
Tohid Moradi Khaneshan
Year 1394
Publish place:
Third National Conference and First International Conference on Applied Research in Electrical, Mechanical and Mechatronics Engineering
Pages:
7
| Language: English
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Conference Paper
A 1.6GHz 16×16-bit Low-Latency Pipelined Booth Multiplier
Authors:
Habib Ghasemizadeh
،
Edris Azadi
،
Khayrollah Hadidi
،
Abdollah Khoei
Year 1390
Publish place:
19th Iranian Conference on Electric Engineering
Pages:
6
| Language: English
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