A Novel CMOS High Speed Very Low Power Current-Mode Multiplier/Divider

In this paper, a novel CMOS high speed very low power low voltage four-quadrant analog multiplier/divider is presented. The design is based on square-difference approach using MOS transistors operating in weak inversion region. The dual translinear loops are the basic building blocks in realization the proposed multiplier/divider circuit. The proposed circuit has been simulated using HSPICE simulator in 0.18 µm TSMC CMOS technology. Simulation results with 0.8V supply voltage shows that the total power consumption is 465nW, total harmonic distortion (THD) is 1.6% (in 1 MHz), maximum linearity error is 3.8% and the -3dB bandwidth is 94.3 MHz.

Keywords:

Current-Mode , MOS Translinear Principle , Weak Inversion , Four-Quadrant Multiplier/Divider