A Review: The Silica Interlayer Engineering of High-k Metal Gate Stack Process

An extensive discussion on the High-k Metal Gate (HKMG) Stack interlayer based-SiO2 for CMOS applications has been reviewed in this paper. The implementation of high-k oxides is a developing strategy to allow more miniaturization of microelectronic components. However, many issues remain to be resolved in the terms of implementation and process integration. One of this challenges is silica (SiO2) interlayer between silicon substrate and high-k oxides that prevent from continue scaling to lower equivalent oxide thicknesses (EOTs). Some techniques to trade these challenges off are investigated andpresented in this work.

Keywords:

HKMG , high-k oxides , silica interlayer , EOTs ,