Fault-Tolerant Techniques for Quantum-dot Cellular Automata Circuits and Systems

This paper explains fault tolerance techniques for Quantum-dot cellular automata which offer remarkable robustness to implement QCA arithmetic circuits. It begins with a study of QCA based design. A classification for fault types is presented and some fault tolerance techniques are examined and their relevance for QCA circuits is evaluated. Finally, it is concluded that a combination of two or more hardware redundancy techniques is needed for tolerating faults in QCA circuits and systems. The proper functionality of the presented design is checked by computer simulations using the QCADesigner tool. Simulation results confirm our claims and their usefulness in designing robust digital circuits.

Keywords:

Quantum-dot cellular Automata , Nanoscale circuits , Fault tolerance , Hardware redundancy