Modified Second Order Generalized Integrator –Frequency Locked Loop Grid Synchronization for Single-Phase Grid-tied System Tuning and Experimentation Assessment

The phase-locked loop (PLL) is applied in grid-tied systems to synchronize converter operation with grid voltage, affecting converter stability and performance. Synchronous reference frame PLL (SRF-PLL) is a popular grid synchronization method due to its simplicity and reliability. Normal SRF-PLL cannot suppress DC offset, causing basic frequency and phase oscillations. When a grid is irregular, its bandwidth should be reduced to ensure acceptable disturbance rejection without sacrificing detection speed. To improve phase-angle detection accuracy and speed, the researchers modified the pre/in-loop filtering stage in advanced PLLs.The capacity to deliver improved dynamic response and reduced settling time without compromising system stability or the ability to eliminate disturbances is a major issue for PLLs. Among different control methods, SOGI-FLL (second-order generalized integrator-based frequency locked loop) had the best performance. It tracks grid voltage frequency precisely even when there is sag, swell, harmonics, frequency fluctuations, etc. In the event of a dc offset, the calculated frequency incorporates low-frequency oscillations. A modified second-order generalized integrator frequency-locked loop (MSOGI-FLL) is presented in this work to address grid voltage anomalies of all types, including dc offset. Using the Waijung Block-set of MATLAB/Simulink, a Modified SOGI-FLL is realized and evaluated by applying abnormal grid voltage situations using a low-cost DSP-based STM۳۲F۴۰۷VGT microcontroller. The results demonstrate MSOGI-better FLL's performance in harsh circumstances.

Keywords:

phase detection , phase-locked loop (PLL) , grid synchronization , STM۳۲F۴۰۷VG microcontroller , WAIJUNG Block-set