A High Speed Residue-to-Binary Converter for Balanced ۴-Moduli Set

Publish Year: 1394
نوع سند: مقاله ژورنالی
زبان: English
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شناسه ملی سند علمی:

JR_JCSE-2-1_004

تاریخ نمایه سازی: 12 دی 1400

Abstract:

The moduli set ۲ n−۱ − ۱, ۲ n+۱ − ۱, ۲ n , ۲ n − ۱ has been recently proposed inliterature for class of ۴n-bit dynamic range in residue number system. Due toonly utilizing modulus in the form of ۲ k − ۱ besides modulo ۲ n , this moduliset enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only doesthe efficiency of a RNS system depend on the residue arithmetic unit but italso is limited to the residue to binary converter. In this paper, a new two levelresidue-to-binary converter architecture based on Mixed Radix Conversion(MRC) is presented for the aforementioned moduli set. The proposed converterincludes two levels of design based on MRC properties. Firstly, the ۳-modulisubset ۲ n−۱ − ۱, ۲ n+۱ − ۱, ۲ n − ۱ is properly organized and as it does notcalculate several values, it results in some cost modifications. Eventually, atwo-moduli set ۲ n−۱ − ۱ ۲ n+۱ − ۱ (۲ n − ۱) , ۲ n is formed to compute thebinary of RNS counterpart. The proposed architecture is shown to be moreefficient both in terms of hardware cost and conversion delay in comparisonwith the related state-of-the-art works.

Authors

MohammadReza Taheri

Faculty of Computer Science and Engineering, Shahid Beheshti University, GC, Tehran, Iran

Nasim Shafiee

Faculty of Computer Science and Engineering, Shahid Beheshti University, GC, Tehran, Iran

Mohammad Esmaeildoust

Faculty of Marine Engineering, Khorramshahr University of Marine Science and Technology, Khuzestan, Iran

Zhale Amirjamshidi

Electronic Engineering Department, Islamic Azad University, Central Tehran Branch, Tehran, Iran

Reza Sabbaghi-nadooshan

Electronic Engineering Department, Islamic Azad University, Central Tehran Branch, Tehran, Iran

Keivan Navi

Faculty of Computer Science and Engineering, Shahid Beheshti University, GC, Tehran, Iran