A High Speed Residue-to-Binary Converter for Balanced ۴-Moduli Set

The moduli set ۲ n−۱ − ۱, ۲ n+۱ − ۱, ۲ n , ۲ n − ۱ has been recently proposed inliterature for class of ۴n-bit dynamic range in residue number system. Due toonly utilizing modulus in the form of ۲ k − ۱ besides modulo ۲ n , this moduliset enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only doesthe efficiency of a RNS system depend on the residue arithmetic unit but italso is limited to the residue to binary converter. In this paper, a new two levelresidue-to-binary converter architecture based on Mixed Radix Conversion(MRC) is presented for the aforementioned moduli set. The proposed converterincludes two levels of design based on MRC properties. Firstly, the ۳-modulisubset ۲ n−۱ − ۱, ۲ n+۱ − ۱, ۲ n − ۱ is properly organized and as it does notcalculate several values, it results in some cost modifications. Eventually, atwo-moduli set ۲ n−۱ − ۱ ۲ n+۱ − ۱ (۲ n − ۱) , ۲ n is formed to compute thebinary of RNS counterpart. The proposed architecture is shown to be moreefficient both in terms of hardware cost and conversion delay in comparisonwith the related state-of-the-art works.

Keywords:

Mixed Radix Conversion , Residue Arithmetic , Residue Number System , Residue-to-Binary Converter