New Multiply-Accumulate Circuits Based on Variable Latency Speculative Architectures with Asynchronous Data Paths

In this paper, variable latency speculative Multiply-Accumulator (MAC) architectures are introduced. The proposed architectures use the idea of integrating the results vectors of multiplier in parallel with the accumulator to create asynchronous data paths design. The proposed variable latency speculative MACs consist of two short and long data paths and a circuit is used to select a suitable path with minimum overhead. In order to investigate variable latency speculative MACs performances, proposed architectures have been synthesized using the Faraday’s ۹۰ nm technology library, for operand lengths ۸, ۱۶ and ۳۲ bits. Obtained results show that the proposed MAC architectures provide a variety of trade-offs in the power-delay-area space that outperform the existing designs that use only the integration technique.

Keywords:

Integration Technique , Multiply-Accumulator , Partial-Product , Variable Latency Speculative Circuits