Low Power Delay Product ۸-bit ALU Design using Decoder and Data Selector

The semiconductor circuits dissipate energy in the form of binary digits. This dissipation of energy is in the form of power consumption. ALU is complex circuit and is one of many components within CPU. It performs mathematical and bitwise operations. This paper proposes a new low power ۸ bit ALU digital circuit for nano scale regions. The proposed ALU has two ۴x۱ data selectors, ۲x۴ decoder and an adder circuit as sub modules. The output of ۲x۴ decoder is connected to ۳ input NAND, AND, OR, XOR gates.  With the help of selection lines of multiplexer the conventional operations of ALU such as logical operations are performed. This proposed ALU caters the need of digital signal processing tools. Present ALU structure is simulated in Linux Computer using Cadence Virtuoso software and implemented in ۱۸۰mm technology. The proposed ALU has delay of ۳۸۶.۰ps and average power of ۶۷۷.۲uW. The power delay product shows ۶۵.۵۸ % improvement when compared to the conventional ۸-bit ALU design

Keywords:

HDL , FPGA , ALU , Decoder , Data Selector , CMOS , FinFET , Power , area , Speed