A Low-Power CMOS Optical Communication Front-End Using a Three-Stage TIA for ۵Gb/s Applications

In this paper, an optical communication receiver system for ۵Gbps applications is proposed concerning power consumption. An inductor-less circuit in three-stages is proposed as the trans-impedance amplifier (TIA), which benefits from the inherent low input resistance of a common gate topology as the first stage. By forming two zeros in this TIA, proper frequency response is obtained while the DC current is reduced. In order to obtain extra gain for the receiver system, three stages of a conventional limiting amplifier (LA) are used. In order to verify the circuit performance, the proposed receiver is simulated in HSPICE using ۹۰nm CMOS technology parameters. The receiver is mathematically studied and is matched with the simulations. Simulations, such as eye-diagram, noise analysis and fabrication process analysis (Monte-Carlo) are done in this paper. The proposed TIA shows ۵۳.۹dbΩ trans-impedance gain, ۳.۵GHz bandwidth, ۱۵.۲pA/√Hz and only ۱.۵۲mw power consumption for ۱.۲v supply voltage, and the receiver system shows ۹۰.۹dbΩ, ۳.۵GHz bandwidth and ۶.۳۴mw power consumption (for ۲stages of TIA and ۳stages of LA) for ۱.۲v supply voltage. Results indicate that the proposed receiver is suitable to work as a low-power ۵Gbps optical communication receiver system.

Keywords:

Low power , en , Trans-impedance amplifier , Limiting Amplifier , optical receiver