A Novel Structure for Optimization of Switching Speed in Nanoscale Tunnel FET

As CMOS (Complementary Metal Oxide Semiconductor) technology is scaled to nanometer regime. Short Channel Effects (SCE) are becoming more and more challenging. To decrease SCE, new device structures have been introduced which unlike MOSFET, operate based on band to band tunneling (BTB) mechanism [1,2]. One of these devices is the Tunneling Field Effect Transistor (TFET) which is in effect a gated p-i-n diode. The current in this device is due to tunneling of the electrons from conduction band to valence band. Due to appealing characteristics of this device, several works has been inclined towards improvement of the Ion/ Ioff ratio [3,4]. For the first time in this paper, we propose an asymmetric oxide thickness approach to reduced Ioff, without any noticeable reduction in Ion.