Design and Simulation of a Fully Integrated, Low-Power, ۲.۵Gb/s Optical Front-End

This paper, describes a CMOS trans-impedance amplifier (TIA) and Limiting Amplifier (LA) for ۲.۵Gb/s, low-power opto-electronic communication receiver systems. The single ended TIA, which benefits form active type of inductors, is designed and simulated using ۰.۱۸µm CMOS process parameters. The proposed circuits are analyzed mathematically and all necessary simulations for proving the proper performance of the proposed TIA stage and the proposed LA stage such as eye-diagram, MONTECARLO and noise analysis are done. Simulation results in HSPICE show the trans-impedance gain of ۴۵.۵dBΩ, frequency bandwidth of ۱.۸۵GHz and power consumption of ۱.۱mW at ۱.۵V supply for the TIA stage and ۸۷dB gain and ۲GHz frequency bandwidth for the whole receiver system, which consumes only ۷.۳mW power. Results indicate that the proposed circuits are suitable to work as a low-power building block as opto-electrical communication receiver.

Keywords:

Trans-impedance amplifier , Limiting Amplifier , Integrated Optical Receiver