Designing Low Dropout Regulator with Low Settling Time, High Power Supply Rejection and Low Line and Load Regulation

Low dropout regulators are one of the most important factures of many portable devices. Thus, consider to the complexity of the circuits and increasing request for portable devices, for increasing battery life and minimizing supply noise, regulators with high efficiency, low output noise and small size is required. In these paper two methods to improve the efficiency of LDO regulators is proposed. First method is increasing gain of error amplifier by using cascode technique, to improve steady-state specification. Second method is using a simple subtractor circuit between error amplifier and pass transistor of LDO regulator to improve power supply rejection, slew-rate and steady-state specification. In addition, both methods are used to achieve area efficiency replacing MIM capacitors with MOS transistor. These low dropout regulators has been simulated in TSMC ۰.۱۸μm CMOS process. Simulation results show enhancement settling time, good line and load regulation and power supply compare with others LDO regulators.

Keywords:

oad regulation , en , Low dropout regulator , Line regulation , Power supply rejection , Slew-rate enhancemen