A Fault-Resistant Architecture for AES S-box Architecture

This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault correction purpose. The newly introduced countermeasure is a fault correction scheme based on DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage becomes high. The control unit holds the previous correct value in the output of our proposed DMR voter in the other pipeline stages as soon as it observes the value ‘۱’ on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provide a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e. ۱۳۷%, and low throughput degradation, i.e. ۱۱.۳%, on the original S-box implementation.

Keywords:

Fault-Resistant , Advanced Encryption Standard (AES) , S-box , High-speed