Design of Low-Power Approximate Logarithmic Multipliers with Improved Accuracy

Approximate computing is considered a promising way to design high-performance and low-power arithmetic units recently. This paper proposes an energy-efficient logarithmic multiplier for error-tolerant applications. The proposed multiplier uses a novel technique to calculate the powers of two products to reduce critical path complexity. Also, a correction term is provided to improve the multiplier accuracy. Additionally, the use of approximate adders in our design is investigated, and optimal truncation length is obtained through simulations. We evaluated our work both in accuracy and hardware criteria. Experiments on a ۱۶-bit proposed multiplier with approximate adder show that power-delay product (PDP) is significantly reduced by ۳۴.۰۵% compared to the best logarithmic multipliers available in the literature, while the mean relative error distance (MRED) is also decreased by ۲۱.۱%. The results of embedding our multiplier in the dequantization step of the JPEG standard show that the image quality is improved in comparison with other logarithmic multipliers. In addition, a subtle drop in image quality compared to utilizing exact multipliers proves the viability of our design.

Keywords:

Logarithmic Multiplier , Approximate Computing , Error-Tolerant