Impact of Gate and Drain Engineering on DC Performance of Charge Plasma TFETs

In this paper, a combined effect of gate and drain workfunctionengineering for enhancing the DC performance of charge plasmaTFETs (CPTFETs) are investigated and proposed. To overcome theissue of ambipolar nature, low threshold voltage and low sub-thresholdslope, we introduce a novel technique (dual work functionality) over thedrain region, with dual work functionality at the gate electrode in acharge plasma based TFET. In this proposed device, the use of dualwork function on drain electrode modulates the bands at the drainchannel interface, which leads to higher barrier for the flow of the holesfrom conduction band of drain to valence band of the channel region,which suppress the ambipolar nature of the device. Furthermore, thepresence of dual work function at the gate electrode improves ON-statecurrent, threshold voltage and sub-threshold slope. Finally, the deviceshows applicability for low power supply voltages as device achievesthe maximum value of high frequency parameters at or below ۰.۶ V ofgate to source voltage.

Keywords:

Gate Engineering , Drain Engineering , DC/RF performance , Charge Plasma TFETs (CPTFETs)