A Low Complexity Multi-Valued Logic Successor and Predecessor in Nanoelectronics

Extremely efficient successor and predecessor circuits are suggested in this article using ۴ CNTFETs. They have much less interconnections and complexity compared to the best previous circuits. The proposed circuits are designed by combining digital and analog techniques for the first time. They can be expanded for all MVLs like ternary, quaternary, pentaternary, and so on. The proposed designs for quaternary logic reduce the transistor count from ۲۵ to ۴ in comparison with the best previous works. Interestingly, in MVLs with more level logics, this difference will increase dramatically. This advantage leads to low complexity and costs. The accurate operation and great performance of introduced circuits are illustrated and their superiority is proved. Additionally, a quaternary half adder is founded on the presented successor and predecessor. The simulation results, which are acquired by comprehensive simulations utilizing Synopsys HSPICE and the ۳۲ nm plenary CNTFET model of Stanford, show that proposed successor and predecessor circuits with only four transistors work accurately. According to these outcomes, in the proposed half-adder, not only the transistor count reduces ۳۲%, but also it has ۴۰% better PDP and ۴۲.۰۵% better EDP in comparison with the best previous work. Also it is more stable against process variation and robust in a wide range of temperature variation.

Keywords:

Multi-valued logic (MVL) , carbon nanotube FET (CNTFET) , nanotechnology , successor/ predecessor circuits