Semiconductor Chipping Improvement via a Full Sandwich Wafer Mounting Technique

Silicon wafers have been widely used in semiconductor manufacturing, and chipping issues often highlighted during wafer dicing which affects device performance and reliability. The phenomenon of chipping has been observed to have detrimental effects on die strength, leading to the potential of crack formation. Cracks became a major concern because its sometimes undetected during testing and had been reported to cause malfunctions at user applications. This study aims to comprehensively analyze the fragile behavior of silicon concerning its chipping and flexural strength performance, providing valuable insights for engineering applications. The research employed new wafer mounting techniques, including chipping analysis, a three-point bending test and scanning electron microscopy (SEM) to reduce silicon die chipping and increase the flexural strength by evaluating the novel semi and full sandwich wafer mounting techniques. The study demonstrated that the implementation of novel full sandwich mounting technique had improved significantly the silicon die chipping and flexural die performance among all the wafer mounting techniques.

Keywords:

chipping , silicon , Three-point bending test , wafer dicing , wafer mounting