Strained Si/SiGe MOSFET for Improved Performance

This paper presents a quantitative study on the device design of ultrathin strained-silicon-on-insulator (strained-SOI) MOSFETs in the sub-100-nm regime aiming atsuppression of short-channel effects (SCEs) and improving the device performance, i.e., break down voltage and sub-threshold swing (SS). In order to improve those parameters, a strainedSi/Si1-xGex is investigated as a replacement for Si technology. We study on the Ge content while the ratio of strained Si and SiGe layers is changing

Keywords:

Silicon on insulator , Strained Si/SiGe on insulator , DIBL , Subthreshold swing