Extended Symmetric Built-In Redundancy Analyzer to Repair Word-Oriented Memories

With the advance of VLSI circuit’s technology and the reduction in the size of devices, the probability of the defects especially in embedded memories has increased. To prevent such flaws, lots of researches have been conducted to design Built-In Self Repair (BISR) circuits so as to prevent the yield drop get to high reliability. This paper will present an at-speed optimal algorithm to repair single-bit errors existing in Word-Oriented memories. Although we use parallel method to get the high analysis speed, the area consumption of the circuit has decreased considerably using our optimal algorithm. The repair rate of the proposed Built-In Redundancy Analyzer (BIRA) is also 100% because we apply the binary search tree as the base of our algorithm. The simulation results andcomparison with other methods show the efficiency of the proposed method

Keywords:

Built-in redundancy analyzer , built-in self-repair , word-oriented memory , Comprehensive Real-time Exhaustive Search Testand Analysis (CRESTA) , extended symmetric BIRA