An ultra low power noise shaping SAR ADC in 90 nm CMOS technology

This paper presents an ultra-low-power successive approximation register (SAR) analogue-to-digitalconverter (ADC) with a new noise shaping technique. The operation of the proposed structure is similar to the firstorder modulator except for its quantizer that is realized by a SAR ADC. Also, it has a simple loop filter topology sothat only a Finite Impulse Response (FIR) filter is used to provide the first-order noise shaping. Due to the highresolution quantizer as well as the small load capacitor, the need for high output swing, fast-settling and high gainOperational Transconductance Amplifier (OTA) for the FIR filter is obviated.The ADC is designed and simulated in 90nm CMOS technology with Spectre simulator. Simulation results shows that the average power consumption of theADC is less than 4.6 μW for a 0.5 V power supply.

An ultra low power noise shaping SAR ADC in 90 nm CMOS technology Keywords:

Ultra low power , SAR ADC , Noise shaping , first order Modulator , CMOS technology