A systolic array architecture for implementing CRC on FPGA technology

Cyclic redundancy codes, CRCs, preserve the integrity of data in storage and transmission applications. CRC can be used either in hardware or software implementations and it is used for error detection in telecommunication systems such as digital video broadcasting, mobile systems etc. In this paper the use of VLSI technology is investigated to speed up cyclic redundancy codes (CRC) circuit. The proposed structure is flexible and the systolic array is used to implement the CRC circuit. This structure can be used for many number of generating polynomials )) ( ( x G . Additionally in this paper a systolic array are proposed for producing D -matrix. But in the previous works it is assumed that is D calculated and stored in memory. By using this unit the delay time for calculating D is substantially decreased.

Keywords:

CRC code , Systolic array , parallel processing , FPGA devices