LPPM: Low Power Partitioned Multiplier

In this paper, a new architecture for low-power multipliers is proposed. The reduction of the power consumption is achieved through reducing the circuit activity at the architecture level. In the proposed technique, depending on the Hamming distance of the current and previous input operands, either original or two's complement form of the operands are used. The multiplier circuit is divided into partitions of smaller multipliers and the approach is applied to lower partitions (bits) of the operand. To assess the efficiency, the technique is applied to JPEG decoder multiplier for some standard pictures. The results show more than 18% switching activity reduction compared to conventional array multiplier.

Keywords:

Low power multiplier , Architecture level power reduction , Switching activity reduction , JPEG decoder.