Analytical Evaluation of a New Error Detection Scheme

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in COTS superscalar processors. The scheme is analytically evaluated based on probabilistic models of control flow errors (CFEs). The results show that the minimum error detection coverage varies between to 92.16% and 96.29%, for different workloads.

Keywords:

COTS Processors , Fault Injection , Error Detection Coverage , Performance Monitoring , Analytical Evaluation