Analytical Evaluation of a New Error Detection Scheme
Publish place: 9th Annual Conference of Computer Society of Iran
Publish Year: 1382
Type: Conference paper
Language: English
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Document National Code:
ACCSI09_073
Index date: 24 January 2008
Analytical Evaluation of a New Error Detection Scheme abstract
Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in COTS superscalar processors. The scheme is analytically evaluated based on probabilistic models of control flow errors (CFEs). The results show that the minimum error detection coverage varies between to 92.16% and 96.29%, for different workloads.
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Analytical Evaluation of a New Error Detection Scheme authors
Amir Rajabzadeh
Department of Computer Engineering Sharif University of Technology
Mirzad Mohandespour
Department of Computer Engineering Sharif University of Technology
Ghassem Miremadi
Department of Computer Engineering Sharif University of Technology
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