CNFET Buffer Insertion along CNT Interconnects for Power Delay Product ’’ Optimization

Resistivity of copper increases with scaling and there is growing demands to identify new wiring solutions for ULSI technologies. Carbon Nanotubes with the special properties is the best candidate for copper replacement in interconnects. As the physical gate length of current devices is reduced, short channel effects degrade performance of the MOSFET transistors. CNFET (Carbon Nanotube Field Effect Transistor) with proper characteristics is a promising suggestion for replacing CMOS transistors. Buffer insertion is performed for delay reduction of interconnects. In this paper, we improve Power Delay Product of semiglobal and global interconnects by application CNT interconnects instead of copper besides CNTFET buffer insertion which is performed between equal portions along interconnects. Extracted results from HSPICE reveals that increasing number of CNFET buffers along semiglobal and global SWCNT interconnects reduce Power Delay product.

CNFET Buffer Insertion along CNT Interconnects for Power Delay Product ’’ Optimization Keywords:

Carbon Nanotube , SWCNTs , CNFET , Buffer Insertion , Power Delay Product Optimization , Semiglobal and Global Interconnect