An investigation into Cluster-based topologies for 3D Networks-on-Chip

A candidate to acquire better performance and package density can be introduced as three-dimensional integrated circuits, which this is compared to traditional two-dimensional. More specifically, a significant performance is obtained for 3D architectures through integrating schemes of Networks-on-Chip and advantages of 3D ICs. Since through-silicon-via (TSV) enables efficient inter-layer communication across multiple stacked layers, it has attracted a lot of interest. Two major architectures to employ TSVs as inter-layer communication channel in 3D architectures include router based and bus based organizations, i.e. the first deteriorates the performance at high injection rates and suffers from poor scalability and the second consumes more power. Wafer utilization and yield is reduced through area overhead of TSVs, found with a huge effect on designing 3D architectures with a large number of TSVs. The present research intends to reduce TSV footprint and power dissipation on each layer with a small performance penalty, for which a novel pipeline bus structure for interlayer communication is proposed to improve the performance by reducing the delay and complexity of traditional bus arbitration

Keywords:

Cluster-based topologies , 3D Networks-on-Chip , inter-layer bus architecture