Presenting a Fault Tolerant Mechanism for Buffering Fault in Network on Chips

As technology scales deep into the nanometer regime, on-chip communicationbecomes more susceptible to transient noise sources, such as crosstalk, externalradiation, and spurious voltage spikes. The Network on chip s modularity andreusability has brought about the use of error control methods to address transienterrors in Network on chip links.In this work, we design a fault tolerance router withefficient area and power dissipated. Actually, we exploit the free virtual channel tostore the redundant data. Virtual channel is used for deadlock avoidance it can beimplement as 2, 4 or 8 channel. The almost time we can find a free channel that wecan use in fault tolerance mechanism. We describe the proposed architecture withVHDL and implemented with synopsis compiler design. We use analytical model toevaluate the fault tolerance. The result shows that we improve the dynamic powerdissipation, area, and reliability.

Keywords:

Network on chip , Buffering , Virtual channel , Fault tolerance router