Design and Simulation A Low-Voltage High Gain CMOS Op Amp for Switched Capacitor in a Digital 90nm CMOS Technology

This paper discusses the design of low-voltage, high gain,fully differential CMOS Op-amp in a low voltage (V DD = 1.0V) 90nm CMOS process. This Op-amp is ideally suitedfor switch-capacitor circuits and simulations show a unity gain bandwidth of 651MHz with 1pF load capacitor and a DC gain of more than 107dB. The phase margin is around 58 o . The circuit topology is a two-stage folded cascode structure with regulated cascodes for gain boosting.

Keywords:

Folded Cascode , Boosting , CMFB