Analog CMOS Kernel for ML Decoding of Convolutional Codes

Decoding of convolutional codes are computationally demanding especially with large code words. It is argued that analog implementations of such decoders can be much more efficient than its digital counterpart. Viterbi Algorithm (VA) is an efficient method to achieve a Maximum Likelihood (ML) solution for convolutional codes. Implementation of Add- Compare-Select which is the kernel of digital realization of the algorithm is still challenging because its effect on overall speed and power consumption of decoder. In this paper a current-based analog CMOS circuit is introduced and demonstrated by its transient and DC simulation results, assuming a 0.35μm CMOS technology. Two main source of errors due to practical limitation of the proposed circuit are also considered. Behavioral simulation shows that performance degradation with respect to standard VA is negligible.

Keywords:

Analog CMOS , Viterbi , WTA , ML Convolutional Decoding