Domino XOR gate design with low power consumption

At the present time, in integrated circuit technology CMOS, low power design is an importantsubject in system design. In order to achieve this target, power consumption must beminimized. In this article a domino XOR gate in 45nm technology is presented. Byeliminating two input complements and preventing the pulse flow to the output node duringthe precharge phase, power consumption in this circuit is reduced.

Domino XOR gate design with low power consumption Keywords:

low power , domino XOR gate , evaluation phase , precharge phase