A Novel Technique for Reducing Subthreshold Current of VLSI Combinational Circuits

In this paper, a new technique for reducing the subthreshold leakage current of CMOS VLSI circuits is proposed. It makes use of the fact that leakage currents of gates are depended on their input patterns. The order of gate input lines is manipulated to reduce the leakage current. The key feature of the method is that it does not have any overhead on the area or the speed. Also, it does not affect the dynamic power consumption of the gate. The execution time for the algorithm determining the primary input order is also very fast. Up to 12% of the static power reduction is achieved by applying this method to ISCAS85 benchmark circuits.

Keywords:

VLSI , Low power Combinational Circuits , Standby power , Subthreshold Leakage Current