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Modeling of Feedback Pulse Jitter Effects on Sigma-Delta Modulator

Publish Year: 1396
Type: Conference paper
Language: English
View: 434

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Document National Code:

ICEEC01_083

Index date: 8 November 2017

Modeling of Feedback Pulse Jitter Effects on Sigma-Delta Modulator abstract

A proposed system level jitter implementation is developed in MATLAB-Simulink to analyze the effects of the feedback jitter on the sigma-delta modulator SNR degradation. Based on the proposed models; also, the tolerable amount of jitter in Continuous-Time Sigma-Delta Modulators are investigated. Two types of rectangular feedback pulse wave, Return to Zero (RZ) and Non-Return to Zero (NRZ) are manipulated with a made up jitter and impose to the different conventional high-order configurations to evaluate the effect of topologies on In-Band Noise. Simulation results confirm that the loop filter with the zeros location optimization result in more than 6dB improvement in clock jitter sensitivity with RZ-DAC. All of the simulations are system level and done in MATLAB-Simulink.

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Modeling of Feedback Pulse Jitter Effects on Sigma-Delta Modulator authors

Reza Chavoshisani

Faculty of Shahid Beheshti University, Tehran, Iran

Omid Hashemipour

Faculty of Shahid Beheshti University, Tehran, Iran