Test Pattern Generation for Integrated Circuits with the Goal of Testing and Optimizing Their Error Detection

The complexity of integrated circuits has increased proportionate to the advances in semiconductors technology, and the process of testing and analyzing VLSI circuits has become significant. The presence of all the advantages of ICs is manifested only through an effective and efficient testing. Today, test pattern generation (ATPG) is done automatically. ATPG systems generate the test pattern using the circuit’s model and its fault model employing a well-known algorithm, and in some cases produce additional information about the type of fault and its location. Given the qualitative and quantitative development of these circuits, the conventional methods are no longer adequate. The patterns extracted from these methods does not display proper fault-finding functionality due to the considerable expansion of the search space commensurate to the IC’s complexity, and when there is need for tests with maximum efficiency, calculation time grows exponentially. Thus in light of the benefit of intelligent methods in efficiently searching a large response space, they are introduced as new solutions for ATPG. Heuristic algorithms have been widely useful in the recent decades in reaching optimization in solving various engineering problems. Thus in this study, the heuristic algorithms of the bee, the gray wolf, the bat, and the grasshopper have been used for the first time in ATPG for synchronous sequential circuits. In test vector generation, these algorithms yield the lowest time and the highest fault coverage and the smallest test string length. In this respect, the employed algorithms display a greater ability in finding the optimal solution compared to other algorithms

Keywords:

Algorithm Test Pattern Generation (ATPG) , Optimization algorithms , Fault coverage , Test vectors