An analysis of Low-dropout regulator Output Designed with TSMC Standard 0.18 μm CMOS

The existing architectures of LDO were classifiedand analyzed. And one overall design principle was illustrated,that is to obtain a constant gate-source-voltage Vgs of the mainpower transistor. A LDO based on this principle was containingan EA, pass transistor and feedback network of the beststructure has been designed with TSMC standard 0.18 μmCMOS process. The input voltage range is 1.2 V to 1.8 V with aminimum dropout voltage of 200 mV. An LDO circuit isanalyzed theoretically, and proved by the simulation of ADS.Simulation show that Dependence of the output voltage to theinput voltage and output load current is low .this LDO havegood parameters which will be examined in this article.Measurement results are in agreement with the analysis also

Keywords:

EA , LDO , pass transistor , PSR