Very High Throughput Implementation of Advanced Encryption Standard (AES) Algorithm on FPGA
Publish place: Signal Processing and Renewable Energy، Vol: 1، Issue: 4
Publish Year: 1396
نوع سند: مقاله ژورنالی
زبان: English
View: 408
This Paper With 8 Page And PDF Format Ready To Download
- Certificate
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
JR_SPRE-1-4_001
تاریخ نمایه سازی: 2 مهر 1398
Abstract:
An Advanced Encryption Standard (AES) algorithm is one of the most popular and most commonly used encryption algorithms. This algorithm can be implemented on microcontroller chips and FPGAs with various specifications. Also, the goals of implementing this algorithm are varied according to the application and requirements. In this paper, a project has been given that output very high data transfer rate equal 192 Gbps on the FPGA of the Virtex-7 (XC7VX330T-3FFG1157) from Xilinx. The extracted results of the implementation of the algorithm in the ISE 14.7 software show the maximum achievable clock frequency 500 MHz, with the parallel implementation of than three AES algorithms cores on a chip, higher speeds are also available.
Keywords:
Authors
Mahdi Rahmanpour
Faculty of Electrical Engineering Islamic Azad University, South Tehran Branch Tehran, Iran
Amir Amirabadi Zavare
Faculty of Electrical Engineering Islamic Azad University, South Tehran Branch Tehran, Iran