Design and Fabrication of a 9–11 GHz Balanced Low Noise Amplifier Using HJFET

This paper describes the design of an X-band balanced low noise amplifier (LNA) using an available HJFET device. The balanced LNA consists of a pair of electrically similar transistors whose input and output signals are divided or combined by 3 dB two-stage Wilkinson power dividers. The proposed balanced LNA is fabricated and measured. The measured results show that the noise figure is 1.30 dB at 10 GHz, the input and output return loss are more than 15 dB and 10 dB, respectively. Also, the gain of 12 dB and gain flatness of ±0.5 dB over the 9-11 GHz frequency range are associated to the balanced LNA. In addition, 15-element small signal equivalent model parameters of the HJFET device used in amplifier design are extracted with an analytical and optimization approache such as Particle Swarm Optimization (PSO) to achieve accurate values. The small-signal model parameters evaluated with the PSO attain 5.9% error compared to the measured data. The validity of the proposed approach is shown by comparing the modeled S-parameter and measured results over 2-18GHz. Simulation results indicate that the PSO approach accurately extracts the small signal model parameters of the HJFET.

Design and Fabrication of a 9–11 GHz Balanced Low Noise Amplifier Using HJFET Keywords:

balanced LNA , heterojunction field , effect transistor (HJFET) , Wilkinson power divider , Particle Swarm Optimization (PSO) , small , signal model