حذف آفست در مقایسه کننده تک طبقه با سرعت مقایسه 800 میلیون نمونه برثانیه با روش تغییر آنالوگ ولتاژ بدنه ترانزیستورهای PMOS

A novel methodology is proposed for offset cancellation in single-stage latched comparators at high comparison speeds. In contrast to the regular methods, high-gain op-amp is not required and the loop accuracy is enhanced by small variations on the body voltages of PMOS devices. Hence, the number of digital signals which are transferred to the analog section are reduced and digital coupling effects are considerably improved. A novel read-out circuit is also proposed which compensates the parasitic capacitance of the next cell and quadruples the fan-out of the comparator, consequently. Worst-Case simulation results confirms that the proposed comparator can detect 1.5mVolts input difference, at all process corners, in presence of 15mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset voltages shows that input referred offset would be improved to 150μV while was 25mVolts at 3σ before the correction. Power consumption is 0.55mW at 800MS/s comparison speed. Post-Layout simulation results are presented using the BSIM3v3 model of a 0.18μm CMOS technology.

Keywords:

Latched comparators , high-speed ADCs , offset cancelled comparators , single-stage comparators