Fault tolerant three dimentional network-on-chip design (3D-NoC): A systematic review

In this paper, we present a systematic literature review of fault-tolerant three -dimensional (3D) network-on-chip (NoC) design. We analyzed several possible faults that need to be considered and compensated during the 3D-NoC design, and also present a technical taxonomy of fault tolerance approaches. Finally, we highlight several open challenges and some possible future research directions in this domain

Keywords:

3D-NoCs , Architecture , Design , Fault tolerant , Systematic literature review