Delay in Fault Tolerant Structures for Nanoscale Gates

Redundancy is a method in the system for designing fault-tolerant structure with the Nanoscale gate in electronic systems. Until now, many ways represented for this purpose, which increases complexity or decreases the reliability of the system. In this paper, we compare two methods for designing a fault-tolerant structure with Nanoscale gates. These ways are NAND Multiplexing (NM) and Averaging Cells (AC). According to simulations to evaluate the area cost and reliability of the gates in [1], it indicates that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this value is exceeded (which is expected for electronic nanotechnologies), AC gates are more reliable at a lower area cost. In this paper, we show comparing the NM and the AC in the aspect of the delay parameter. It indicates that the AC method has a constant delay, but the delay of the NM system will rise with increasing redundancy. Overally, the overhead of the AC method for designing a fault-tolerant system with the Nanoscale gate is lower than the NM method in the aspect of the area and delay time with better reliability.

Keywords:

Fault-Tolerance , NAND Multiplexing , Averaging Cell , Delay , reliability.