Design of a New Low Power Nano Flip-Flop With Low Leakage Current
Publish place: 1st National Conference on Nano Science and Technology
Publish Year: 1389
Type: Conference paper
Language: English
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Document National Code:
NNTC01_518
Index date: 30 October 2010
Design of a New Low Power Nano Flip-Flop With Low Leakage Current abstract
In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is increase potential of sourse and increase threshold voltage techniques. With decrease dimension and reduction of working voltage and threshold voltage in CMOS technology, increase the leakage currents exponentially and share of it in total power consumption is high, In these conditions Disable inactive parts of the circuit can be effective in reduce power consumption. In this paper with review the methods of leakage current control, flip-flop is introduced that can receive data in both clock edges. The low number of transistor, low capacitor, low current leakage and low power consumption are advantages accruning of the proposed structure is low.
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Design of a New Low Power Nano Flip-Flop With Low Leakage Current authors
Milad Kaboli
Department of Electrical Engineering, Islamic Azad University, Shoushtar Branch, Shoushtar
Behzad Ghanavati
Department of Electrical Engineering, Islamic Azad University, Mahshahr Branch, Mahshahr, Iran
Seyed Vali Heydari
Department of Electrical Engineering, Islamic Azad University, Mahshahr Branch, Mahshahr, Iran