Design of a New Low Power Nano Flip-Flop With Low Leakage Current

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is increase potential of sourse and increase threshold voltage techniques. With decrease dimension and reduction of working voltage and threshold voltage in CMOS technology, increase the leakage currents exponentially and share of it in total power consumption is high, In these conditions Disable inactive parts of the circuit can be effective in reduce power consumption. In this paper with review the methods of leakage current control, flip-flop is introduced that can receive data in both clock edges. The low number of transistor, low capacitor, low current leakage and low power consumption are advantages accruning of the proposed structure is low.

Keywords:

Low power flip-flop , Low leakage current , Low power Consumption , D flip-flop , Control leakage current