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Title

Design of a New Low Power Nano Flip-Flop With Low Leakage Current

Year: 1389
COI: NNTC01_518
Language: EnglishView: 1,705
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Authors

Milad Kaboli - Department of Electrical Engineering, Islamic Azad University, Shoushtar Branch, Shoushtar
Behzad Ghanavati - Department of Electrical Engineering, Islamic Azad University, Mahshahr Branch, Mahshahr, Iran
Seyed Vali Heydari - Department of Electrical Engineering, Islamic Azad University, Mahshahr Branch, Mahshahr, Iran

Abstract:

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is increase potential of sourse and increase threshold voltage techniques. With decrease dimension and reduction of working voltage and threshold voltage in CMOS technology, increase the leakage currents exponentially and share of it in total power consumption is high, In these conditions Disable inactive parts of the circuit can be effective in reduce power consumption. In this paper with review the methods of leakage current control, flip-flop is introduced that can receive data in both clock edges. The low number of transistor, low capacitor, low current leakage and low power consumption are advantages accruning of the proposed structure is low.

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Paper COI Code

This Paper COI Code is NNTC01_518. Also You can use the following address to link to this article. This link is permanent and is used as an article registration confirmation in the Civilica reference:

https://civilica.com/doc/104088/

How to Cite to This Paper:

If you want to refer to this Paper in your research work, you can simply use the following phrase in the resources section:
Kaboli, Milad and Ghanavati, Behzad and Heydari, Seyed Vali,1389,Design of a New Low Power Nano Flip-Flop With Low Leakage Current,1st National Conference on Nano Science and Technology,Yazd,https://civilica.com/doc/104088

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