A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

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A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

Publish place: Journal of Electrical and Computer Engineering Innovations، Vol: 7، Issue: 2

Publish Year: 1398

نوع سند: مقاله ژورنالی

زبان: English

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لینک ثابت به این Paper:

https://civilica.com/doc/1124619

شناسه ملی سند علمی:

JR_JECEI-7-2_005

تاریخ نمایه سازی: 5 آذر 1399

Abstract:

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Keywords:

Delta-sigma modulation , Gated Switched-Ring Oscillator (GSRO) , Multi-stage-noise-shaping (MASH) , Oversampling , Voltage-Controlled Oscillator (VCO)

Authors

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Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.

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Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.

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Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.

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