Modular Parallel-Prefix Arithmetic Circuits design based on Reversible Computing

Power consumption in today's modern high-performance computing systems is one of the most important design issues. Reversible computations have attracted a lot of attention compared to classical calculations due to their ability to reduce energy loss and power consumption of circuits. The reversible logic has applications in various technologies such as quantum circuits, low power circuit design, nanotechnology, optical information processing, DNA and bioinformatics calculations. Adder and multiplier are the main parts of any computing systems and therefore play an important role in the performance of reversible computations. Features of a reversible ripple-carry adder are high quantum depth, low quantum cost, low garbage outputs, and low constant input bits. In this paper, a new reversible kogge-Stone parallel-prefix adder and multiplier is proposed for modulo ۲n±۱. The analysis shows that the reversible-logic parallel-prefix adder and multiplier are faster and have the lowest depth compared to the reversible-logic-based ripple-carry adder and multiplier.

Keywords:

Reversible logic , Modular adder , Modular multiplier , Parallel-Prefix Adder