An Ultra-High-Speed Low-Power CMOS 1-Bit Fast Full Adder Cell Using Gate-Diffusion Input Technique

In this paper a new high speed 1-bit fast full adder cell with the least chip area and using the GDI technique is proposed. Simulation results performed by HSPICE in 0.35 μm CMOS process illustrate the superiority of the resulting proposed adder cell against several conventional CMOS 1-bit full adder cells in terms of gate area, delay, power dissipation, and PDP. Simulation results show that the proposed adder has the least propagation delay of 151.65 psec and power dissipation of 5.58 μW in a supply voltage of 2.8 V.

An Ultra-High-Speed Low-Power CMOS 1-Bit Fast Full Adder Cell Using Gate-Diffusion Input Technique Keywords:

Full Adder , GDI , Low-Power , PDP , Propagation Delay