A Novel Low-Power Approximate Logarithmic Multiplier

Logarithmic multipliers are promising to improve hardware measures significantly at the cost of slight accuracy degradation. Logarithmic multipliers convert multiplication into the shift and add operations. This paper has proposed a new logarithmic multiplier to reduce power and delay for applications with fewer accuracy restrictions. Moreover, the error has reduced in comparison to works similar to our work. We have used a novel method to compute the powers of two products for critical path and hardware area reduction. Furthermore, compared to recent work that uses nearest one detector, abstractors are replaced with XORs, and for precision improvement, an additional term is considered. Our proposed method is used to design a ۱۶-bit multiplier. Error analysis and simulations are done, and results show that our work reduces power by ۴۲.۹% and improves accuracy by about ۲۵.۶% compared to the design in the literature, which has state-of-the-art accuracy. While many previous works had a single-sided error, our work has a double-sided error distribution, which cancels error accumulation in some applications. Evaluation of our proposed method in the JPEG standard shows that this multiplier is practical in real-world applications.

Keywords:

Logarithmic Multiplier , Approximate Computing , Error-Tolerant