Energy-Efficient Variation-Resilient High-Throughput Processor Design
Publish Year: 1401
نوع سند: مقاله ژورنالی
زبان: English
View: 121
This Paper With 12 Page And PDF Format Ready To Download
- Certificate
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
JR_JECEI-10-2_004
تاریخ نمایه سازی: 20 تیر 1401
Abstract:
kground and Objectives: The future demands of multimedia and signal processing applications forced the IC designers to utilize efficient high performance techniques in more complex SoCs to achieve higher computing throughput besides energy/power efficiency improvement. In recent technologies, variation effects and leakage power highly affect the design specifications and designers need to consider these parameters in design time. Considering both challenges as well as boosting the computation throughput makes the design more difficult.Methods: In this article, we propose a simple serial core for higher energy/power efficiency and also utilize data level parallel structures to achieve required computation throughput.Results: Using the proposed core we have ۳۵% (۷۵%) energy (power) improvement and also using parallel structure results in ۸x higher throughput. The proposed architecture is able to provide ۷۶ MIPS computation throughput by consuming only ۲.۷ pj per instruction. The outstanding feature of this processor is its resiliency against the variation effects.Conclusion: Simple serial architecture reduces the effect of variations on design paths, furthermore, the effect of process variation on throughput loss and energy dissipation is negligible and almost zero. Proposed processor architecture is proper for energy/power constrained applications such as internet of things (IoT) and mobile devices to enable easy energy harvesting for longer lifetime.
Keywords:
Authors
A. Teymouri
Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.
H. Dorosti
Department of Computer Systems Architecture, Faculty of Computer Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran.
M. Ersali Salehi Nasab
Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.
S.M. Fakhraie
Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.
مراجع و منابع این Paper:
لیست زیر مراجع و منابع استفاده شده در این Paper را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود Paper لینک شده اند :