A CAD tool for low power scalable floating-point adder generator

The paper describes a CAD tool written in C++ that ge nerates VHDL code for a scalable, low power floating-point adder. The tool produces two output architectures depending on the specified objective function. Area, as well as delay and power can be optimized and targeted to a scalable architecture. A novel low power floating-point architecture is described. An example is given to show the flexibility and the usefulness of the CAD tool in producing synthesizeable architectures.

Keywords:

Floating Point Addition , Low Power , Digital Synthesis CAD